PCIe Gen5 MCIO 8i (SFF-TA-1016) & M7 Low-Dk PCB Coupon 85Ω Differential Impedance TDR & 4-Port S-Parameter (S4P) Verification
| test_method_clause | PCI-SIG PCIe 5.0 CEM §4.3 / SFF-TA-1016 Rev 1.4 / EIA-364-108 / IPC-TM-650 2.5.5.7a TDR (30 ps 20%–80% rise time) & IEEE 370-2020 2x-Thru De-Embedded 4-Port VNA S4P (10 MHz–32 GHz) |
|---|---|
| hw_fw_revision | HW-REV-B2 / N/A-PASSIVE-30AWG-TWINAX + M7-18L-HVLP2-COUPON-REV-A4 |
| sample_lot_scope | Lot 2026-Q3-SZ-014 (n=25 MCIO 8i 74-pin assemblies + 6 IPC-2141A stripline coupons, 100% pinout & TDR sweep) · test_date: 2026-09-18 |
| pass_criteria_vs_result | Pass criteria: 85 Ohm +/- 5% (80.75-89.25 Ohm), Insertion Loss <= -7.5 dB @ 16 GHz, Return Loss SDD11 <= -12.0 dB; Result: 84.6 Ohm mean, -6.1 dB @ 16 GHz, SDD11 -15.4 dB (PASS) |
| report_sha256 & disclaimer |
e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855SHA-256 digest of the raw Touchstone (.s4p) archive and TDR waveform log; not a statutory or PCI-SIG Integrators List certification. |
| applicability_limitations | Applies strictly to Lot 2026-Q3-SZ-014 0.5m-0.8m twinax routing; host retimer channel equalization varies by motherboard topology. |