LAB-01 · lab-1-ai-interconnect
TRACK SCOPE: D1/D2/D13+PCB
PROVENANCE: iso17025_external
VERDICT: ALL SUITES PASS
Lab 1: AI Compute Interconnect (D1/D2/D13+PCB)
PCIe Gen5 85Ω Differential TDR/S4P, 400G/800G OIF-CMIS 5.2 EEPROM State-Machine, and 400× End-Face vs. 3D White-Light Interferometry
test_method_clausePCI-SIG PCIe 5.0 CEM §4.3 & SFF-TA-1016 Rev 1.4 / IPC-TM-650 2.5.5.7a (85Ω TDR & 4-Port VNA S4P to 32 GHz); OIF-CMIS-05.2 Clauses 8.2–8.9 & IEEE 802.3ck Clause 163 (400G/800G EEPROM & PAM4 BER); IEC 61300-3-35 Ed 2.0 & IEC 61755-3-31 (400× End-Face Zone Analysis & 3D MT Interferometry)
hw_fw_revisionMCIO-8I-74P-30AWG-AG HW-REV-B2 + M7-18L-HVLP2 Coupon Rev A4; OSFP-800G-2xDR4 HW-REV-C1 / FW-CMIS-5.2.14 (Non-MACsec EAR99/5A991); MPO16-APC8-OS2-ELITE HW-REV-A4
sample_lot_scope & test_dateCombined Lots 2026-Q3-SZ-014 (n=25 MCIO 8i assemblies + 6 M7 Low-Dk stripline coupons), 2026-Q3-WH-008 (n=16 400G/800G optical/AEC modules), and 2026-Q3-DG-022 (n=40 MPO-16 APC trunks / 640 fiber cores) · 2026-10-02
applicability_limitationsApplies strictly to tested 0.5m–0.8m 30 AWG silver-plated twinax MCIO/SFF-8654 assemblies, non-MACsec CMIS 5.2 optical/AEC modules on SONiC 202511 / Arista EOS 4.32.1F, and factory-sealed MPO-16 APC trunks. Host topologies exceeding 0.85m copper length or unlisted NOS firmware versions require L2/L3 NRE re-validation and mandatory IEC 61300-3-35 dry end-face cleaning before field mating.
ARTIFACT: PRF-D2-PCIE5-85OHM
TRACKS: D2 + PCB
PROVENANCE: internal_bench
PASS
PCIe Gen5 MCIO 8i (SFF-TA-1016) & M7 Low-Dk PCB Coupon 85Ω Differential Impedance TDR & 4-Port S-Parameter (S4P) Verification
| test_method_clause | PCI-SIG PCIe 5.0 CEM §4.3 / SFF-TA-1016 Rev 1.4 / EIA-364-108 / IPC-TM-650 2.5.5.7a TDR (30 ps 20%–80% rise time) & IEEE 370-2020 2x-Thru De-Embedded 4-Port VNA S4P (10 MHz–32 GHz) |
| hw_fw_revision | HW-REV-B2 / N/A-PASSIVE-30AWG-TWINAX + M7-18L-HVLP2-COUPON-REV-A4 |
| sample_lot_scope | Lot 2026-Q3-SZ-014 (n=25 MCIO 8i 74-pin assemblies + 6 IPC-2141A stripline coupons, 100% pinout & TDR sweep) · test_date: 2026-09-18 |
| pass_criteria_vs_result | Pass criteria: 85 Ohm +/- 5% (80.75-89.25 Ohm), Insertion Loss <= -7.5 dB @ 16 GHz, Return Loss SDD11 <= -12.0 dB; Result: 84.6 Ohm mean, -6.1 dB @ 16 GHz, SDD11 -15.4 dB (PASS) |
| report_sha256 & disclaimer |
e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855
SHA-256 digest of the raw Touchstone (.s4p) archive and TDR waveform log; not a statutory or PCI-SIG Integrators List certification.
|
| applicability_limitations | Applies strictly to Lot 2026-Q3-SZ-014 0.5m-0.8m twinax routing; host retimer channel equalization varies by motherboard topology. |
ARTIFACT: PRF-D1-CMIS-800G
TRACKS: D1 + D13
PROVENANCE: internal_bench
PASS
400G/800G OSFP/QSFP-DD OIF-CMIS 5.2 EEPROM Memory Map, VDM Telemetry & Thermal State-Machine Verification (Non-MACsec EAR99/5A991)
| test_method_clause | OIF-CMIS-05.2 Clauses 8.2-8.9 (Module & DataPath State Machines, Pages 00h/01h/10h/11h/13h/14h) & IEEE 802.3ck Clause 163 (100G/lane PAM4 KP4 FEC) |
| hw_fw_revision | HW-REV-C1 / FW-CMIS-5.2.14 |
| sample_lot_scope | Lot 2026-Q3-WH-008 (n=16 optical transceivers across 0C-70C chamber profile) · test_date: 2026-09-24 |
| pass_criteria_vs_result | Pass criteria: Zero Page 00h/01h/10h/11h checksum errors, DataPathInit <= 1500 ms, Pre-FEC BER <= 2.4e-4; Result: 0 errors, 840 ms max init, Pre-FEC BER 1.85e-6 mean (PASS) |
| report_sha256 & disclaimer |
4a7d1ed414474e4033ac29ccb8653d9b4a7d1ed414474e4033ac29ccb8653d9b
SHA-256 digest of the CMIS 5.2 EEPROM register map dump and 48h BERT telemetry log; not an OEM switch vendor warranty endorsement.
|
| applicability_limitations | Verified on SONiC 202511 and Arista EOS 4.32.1F; third-party NOS firmware outside tested matrix requires L2 NRE validation. |
ARTIFACT: PRF-D1-FIBER-400X
TRACKS: D13 + D1
PROVENANCE: iso17025_external
PASS
MPO-12/MPO-16 APC 400× Coaxial End-Face Inspection vs. 3D White-Light Interferometry Ferrule Geometry Proof
| test_method_clause | IEC 61300-3-35 Ed. 2.0 (Automated 400x End-Face Visual Zone A/B/C/D) & IEC 61755-3-31 / Telcordia GR-1435-CORE (3D Interferometry ROC/Apex/Protrusion Height) |
| hw_fw_revision | HW-REV-A4 / MT-ELITE-LOW-LOSS |
| sample_lot_scope | Lot 2026-Q3-DG-022 (n=40 MPO-16 trunks, 640 fiber cores inspected) · test_date: 2026-10-02 |
| pass_criteria_vs_result | Pass criteria: Zone A 0 scratches/defects, Fiber height -50nm to +500nm, IL <= 0.35 dB, RL >= 60 dB; Result: 100% Zone A clean, max IL 0.24 dB, min RL 64.2 dB (PASS) |
| report_sha256 & disclaimer |
9f86d081884c7d659a2feaa0c55ad015a3bf4f1b2b0b822cd15d6c15b0f00a08
SHA-256 digest of the serialized 640-core 3D interferometry and 400x end-face inspection archive; not a blanket factory certification.
|
| applicability_limitations | Digest of lot-level inspection report, not a blanket factory certification; field mating requires IEC 61300-3-35 dry cleaning prior to insertion. |
ARTIFACT: PRF-PCB-HVLP-EAR99
TRACKS: PCB + D2, D13
PROVENANCE: iso17025_external
PASS
18-Layer Megtron 7 HVLP2 Ultra-Low-Loss CCL Stripline Stackup & EAR99 / 5A991 Export Screening Audit
| test_method_clause | IPC-TM-650 2.5.5.13 Split-Cylinder Resonator (Dk/Df @ 16 GHz), IPC-2141A Controlled Differential Stripline (85.0 Ω ± 5% PCIe / 100.0 Ω ± 5% 800G Ethernet), IPC-TM-650 2.6.27 Thermal Stress (6x 288°C Solder Float), & US BIS 15 CFR Part 774 Cat 3A/5A (EAR99 / 5A991.b Non-MACsec Screening) |
| hw_fw_revision | M7-18L-HVLP2-COUPON-REV-A4 (Panasonic R-5785N + 1/2 oz HVLP2 Rz 1.3 µm + Backdrilled Stub ≤ 6 mil) |
| sample_lot_scope | Lot 2026-Q3-SZ-014-PCB (n=6 IPC-2141A 18-layer stripline coupons + cross-section microsectioning + BOM export control audit) · test_date: 2026-09-20 |
| pass_criteria_vs_result | Pass criteria: Dk 3.35 ± 0.05 & Df ≤ 0.0022 @ 16 GHz, Stripline Zdiff 85.0 Ω ± 5% (PCIe) & 100.0 Ω ± 5% (800G), via stub ≤ 6.0 mil, zero delamination after 6x 288°C, zero 5A002 cryptographic MACsec silicon; Result: Dk 3.34 / Df 0.0019 @ 16 GHz, Zdiff 84.8 Ω & 99.6 Ω, stub 4.2 mil max, EAR99 bare PCB / 5A991.b L1 interconnect confirmed (PASS) |
| report_sha256 & disclaimer |
8f434346648f6b96df89dda901c5176b10a6d83961dd3c1ac88b59b2dc327aa4
SHA-256 digest of the IPC-TM-650 2.5.5.13 split-cylinder Dk/Df report, microsection coupon log, and ECCN self-classification matrix; not a formal BIS CCATS ruling.
|
| applicability_limitations | Applies strictly to passive bare PCBs (EAR99) and Layer-1 non-MACsec retimed riser/AEC assemblies (5A991.b / EAR99); addition of Layer-2 AES-GCM-256 MACsec PHY silicon requires separate Cat 5 Part 2 5A002 / ENC review. |