{ "schema_version": "2.0.0", "lab_id": "lab-1-ai-interconnect", "canonical_url": "https://asaptic.com/proof-labs/ai-compute-interconnect/", "publisher": { "name": "Asaptic", "url": "https://asaptic.com/" }, "benches": { "bench1_pcie": { "protocols": [ { "id": "gen5_32g", "label": "PCIe Gen5 (32.0 GT/s NRZ · 16 GHz Nyquist)", "max_total_loss_db": 36.0, "max_harness_loss_db": 7.5, "modulation": "NRZ" }, { "id": "gen6_64g", "label": "PCIe Gen6 (64.0 GT/s PAM4 · 16 GHz Nyquist)", "max_total_loss_db": 32.0, "max_harness_loss_db": 6.5, "modulation": "PAM4 (FLIT)" } ], "connectors": [ { "id": "mcio_8i", "label": "MCIO 8i 74-Pin (SFF-TA-1016 Rev 1.4)", "pair_loss_db": 0.75, "z_diff_ohm": 85.0 }, { "id": "slimsas_8i", "label": "SlimSAS 8i 74-Pin (SFF-8654)", "pair_loss_db": 0.92, "z_diff_ohm": 85.0 }, { "id": "oculink_4i", "label": "OCuLink 4i 42-Pin (SFF-8611)", "pair_loss_db": 1.05, "z_diff_ohm": 85.0 } ], "gauges": [ { "id": "30awg_ag", "label": "30 AWG Silver-Plated Solid Twinax (Ultra-Low Skew)", "db_per_m_16ghz": 6.2 }, { "id": "28awg_ag", "label": "28 AWG Silver-Plated Twinax (Low-Loss Trunk)", "db_per_m_16ghz": 5.1 }, { "id": "32awg_ag", "label": "32 AWG High-Density Flex Twinax", "db_per_m_16ghz": 7.8 } ], "pcb_grades": [ { "id": "m7_hvlp2", "label": "Megtron 7 + HVLP2 (Dk 3.35, Df 0.0020 @ 16 GHz)", "db_per_inch_16ghz": 0.68 }, { "id": "m8_hvlp3", "label": "Megtron 8 + HVLP3 (Dk 3.20, Df 0.0014 @ 16 GHz)", "db_per_inch_16ghz": 0.54 }, { "id": "m6_vlp", "label": "Megtron 6 + VLP (Dk 3.60, Df 0.0040 @ 16 GHz)", "db_per_inch_16ghz": 0.92 } ] }, "bench2_800g": { "profiles": [ { "id": "osfp_800g_dac_1m", "form_factor": "OSFP-800G (8x100G PAM4)", "media_type": "Passive Twinax DAC (26 AWG)", "length_m": 1.0, "cmis_rev": "OIF-CMIS 5.2 (Page 00h/01h Passive)", "channel_il_26g_db": 14.8, "post_eq_ber": "4.2e-14 (<1e-12 Pre-FEC Bench)", "raw_kp4_ber": "1.1e-7", "eye_height_mv": 48.5, "eye_width_ui": 0.34, "power_w": 0.1, "ear_class": "EAR99 (Passive Copper)", "verdict": "PASS" }, { "id": "qsfpdd_800g_dac_2m", "form_factor": "QSFP-DD800 (8x100G PAM4)", "media_type": "Passive Twinax DAC (26 AWG)", "length_m": 2.0, "cmis_rev": "OIF-CMIS 5.2 (Page 00h/01h Passive)", "channel_il_26g_db": 19.4, "post_eq_ber": "8.6e-13 (<1e-12 Pre-FEC Bench)", "raw_kp4_ber": "8.4e-6", "eye_height_mv": 34.0, "eye_width_ui": 0.27, "power_w": 0.1, "ear_class": "EAR99 (Passive Copper)", "verdict": "PASS" }, { "id": "osfp_800g_aec_3m", "form_factor": "OSFP-800G (8x100G PAM4)", "media_type": "Active Electrical Cable (AEC 7nm Retimed DSP)", "length_m": 3.5, "cmis_rev": "OIF-CMIS 5.2.14 (Pages 00h–14h VDM)", "channel_il_26g_db": 26.2, "post_eq_ber": "1.2e-14 (<1e-12 Pre-FEC Bench)", "raw_kp4_ber": "1.85e-6", "eye_height_mv": 56.0, "eye_width_ui": 0.38, "power_w": 9.8, "ear_class": "5A991.b / EAR99 (Non-MACsec L1 DSP)", "verdict": "PASS" }, { "id": "qsfp112_400g_aec_5m", "form_factor": "QSFP112-400G (4x100G PAM4)", "media_type": "Active Electrical Cable (AEC 7nm Retimed DSP)", "length_m": 5.0, "cmis_rev": "OIF-CMIS 5.2.14 (Pages 00h–14h VDM)", "channel_il_26g_db": 28.1, "post_eq_ber": "3.5e-13 (<1e-12 Pre-FEC Bench)", "raw_kp4_ber": "4.1e-6", "eye_height_mv": 49.0, "eye_width_ui": 0.35, "power_w": 5.4, "ear_class": "5A991.b / EAR99 (Non-MACsec L1 DSP)", "verdict": "PASS" }, { "id": "osfp_800g_2xdr4_opt", "form_factor": "OSFP-800G-2xDR4 (1310nm EML)", "media_type": "Optical Transceiver (Dual MPO-12 APC 500m)", "length_m": 500.0, "cmis_rev": "OIF-CMIS 5.2.14 (Pages 00h–14h VDM)", "channel_il_26g_db": 3.2, "post_eq_ber": "9.0e-15 (<1e-12 Pre-FEC Bench)", "raw_kp4_ber": "6.2e-7", "eye_height_mv": 62.0, "eye_width_ui": 0.41, "power_w": 15.2, "ear_class": "5A991.b (Non-MACsec L1 PAM4 DSP)", "verdict": "PASS" }, { "id": "unretimed_dac_4m_fail", "form_factor": "OSFP-800G (8x100G PAM4)", "media_type": "Over-Length Passive DAC (28 AWG Unretimed — Stress Reject)", "length_m": 4.0, "cmis_rev": "OIF-CMIS 5.2 (Passive)", "channel_il_26g_db": 33.8, "post_eq_ber": "6.8e-9 (EXCEEDS 1e-12 BENCH)", "raw_kp4_ber": "4.9e-4 (FEC OVERFLOW)", "eye_height_mv": 9.5, "eye_width_ui": 0.08, "power_w": 0.1, "ear_class": "EAR99", "verdict": "FAIL — REQUIRES AEC RETIMER" } ] }, "bench3_fiber": { "presets": [ { "id": "lot_dg022_pass", "label": "Lot 2026-Q3-DG-022 MPO-16 APC Elite (Production Reference — PASS)", "zone_a_scratches": 0, "zone_a_defects": 0, "zone_b_scratches_gt3um": 0, "zone_b_defects_2_5um": 1, "zone_b_defects_gt5um": 0, "protrusion_nm": 210, "adj_delta_nm": 190, "apc_angle_deg": 8.03, "il_db": 0.18, "rl_db": 64.2 }, { "id": "field_uncleaned_fail", "label": "Uncleaned Field Ferrule (Core Zone A Contamination — FAIL)", "zone_a_scratches": 1, "zone_a_defects": 2, "zone_b_scratches_gt3um": 2, "zone_b_defects_2_5um": 4, "zone_b_defects_gt5um": 1, "protrusion_nm": 240, "adj_delta_nm": 210, "apc_angle_deg": 8.05, "il_db": 0.62, "rl_db": 51.0 }, { "id": "undercut_ferrule_fail", "label": "MT Ferrule Fiber Undercut (-95 nm Air-Gap Reflection — FAIL)", "zone_a_scratches": 0, "zone_a_defects": 0, "zone_b_scratches_gt3um": 0, "zone_b_defects_2_5um": 0, "zone_b_defects_gt5um": 0, "protrusion_nm": -95, "adj_delta_nm": 380, "apc_angle_deg": 7.72, "il_db": 0.44, "rl_db": 54.8 } ] }, "bench4_ccl": { "laminates": [ { "id": "megtron7", "name": "Panasonic Megtron 7 (R-5785N)", "dk_16g": 3.35, "df_16g": 0.002, "tg_c": 210, "grade": "Ultra-Low-Loss (PCIe Gen5/Gen6 & 800G)" }, { "id": "megtron8", "name": "Panasonic Megtron 8 (R-5795)", "dk_16g": 3.2, "df_16g": 0.0014, "tg_c": 220, "grade": "Extreme-Low-Loss (PCIe Gen6 & 1.6T)" }, { "id": "tachyon100g", "name": "Isola Tachyon 100G", "dk_16g": 3.02, "df_16g": 0.0021, "tg_c": 210, "grade": "Ultra-Low-Loss Backplane" }, { "id": "tu883", "name": "TUC TU-883 (SP)", "dk_16g": 3.4, "df_16g": 0.0022, "tg_c": 210, "grade": "Ultra-Low-Loss AI OAM Riser" }, { "id": "megtron6", "name": "Panasonic Megtron 6 (R-5775)", "dk_16g": 3.6, "df_16g": 0.004, "tg_c": 185, "grade": "Very-Low-Loss (PCIe Gen4/Gen5 Short Reach)" } ], "foils": [ { "id": "hvlp3", "name": "HVLP3 Copper Foil (Rz ≤ 1.0 µm)", "roughness_rz_um": 0.9, "skin_factor": 1.04 }, { "id": "hvlp2", "name": "HVLP2 Copper Foil (Rz ≤ 1.5 µm)", "roughness_rz_um": 1.3, "skin_factor": 1.1 }, { "id": "vlp", "name": "VLP Copper Foil (Rz ≤ 2.5 µm)", "roughness_rz_um": 2.2, "skin_factor": 1.24 }, { "id": "rtf", "name": "Standard RTF Foil (Rz ~ 3.8 µm — High Skin Loss)", "roughness_rz_um": 3.8, "skin_factor": 1.48 } ] }, "artifact_1d_ccl": { "artifact_id": "PRF-PCB-HVLP-EAR99", "lab_id": "lab-1-ai-interconnect", "track_code": "PCB", "secondary_tracks": [ "D2", "D13" ], "title": "18-Layer Megtron 7 HVLP2 Ultra-Low-Loss CCL Stripline Stackup & EAR99 / 5A991 Export Screening Audit", "test_method_clause": "IPC-TM-650 2.5.5.13 Split-Cylinder Resonator (Dk/Df @ 16 GHz), IPC-2141A Controlled Differential Stripline (85.0 Ω ± 5% PCIe / 100.0 Ω ± 5% 800G Ethernet), IPC-TM-650 2.6.27 Thermal Stress (6x 288°C Solder Float), & US BIS 15 CFR Part 774 Cat 3A/5A (EAR99 / 5A991.b Non-MACsec Screening)", "hw_fw_revision": "M7-18L-HVLP2-COUPON-REV-A4 (Panasonic R-5785N + 1/2 oz HVLP2 Rz 1.3 µm + Backdrilled Stub ≤ 6 mil)", "sample_lot_scope": "Lot 2026-Q3-SZ-014-PCB (n=6 IPC-2141A 18-layer stripline coupons + cross-section microsectioning + BOM export control audit)", "test_date": "2026-09-20", "pass_criteria_vs_result": "Pass criteria: Dk 3.35 ± 0.05 & Df ≤ 0.0022 @ 16 GHz, Stripline Zdiff 85.0 Ω ± 5% (PCIe) & 100.0 Ω ± 5% (800G), via stub ≤ 6.0 mil, zero delamination after 6x 288°C, zero 5A002 cryptographic MACsec silicon; Result: Dk 3.34 / Df 0.0019 @ 16 GHz, Zdiff 84.8 Ω & 99.6 Ω, stub 4.2 mil max, EAR99 bare PCB / 5A991.b L1 interconnect confirmed (PASS)", "lab_provenance": "iso17025_external", "report_sha256": "8f434346648f6b96df89dda901c5176b10a6d83961dd3c1ac88b59b2dc327aa4", "report_sha256_disclaimer": "SHA-256 digest of the IPC-TM-650 2.5.5.13 split-cylinder Dk/Df report, microsection coupon log, and ECCN self-classification matrix; not a formal BIS CCATS ruling.", "applicability_limitations": "Applies strictly to passive bare PCBs (EAR99) and Layer-1 non-MACsec retimed riser/AEC assemblies (5A991.b / EAR99); addition of Layer-2 AES-GCM-256 MACsec PHY silicon requires separate Cat 5 Part 2 5A002 / ENC review." } }, "lab_summary": { "lab_id": "lab-1-ai-interconnect", "lab_code": "LAB-01", "track_scope": "D1/D2/D13+PCB", "tracks": [ "D1", "D2", "D13", "PCB" ], "title": "Lab 1: AI Compute Interconnect (D1/D2/D13+PCB)", "subtitle": "PCIe Gen5 85Ω Differential TDR/S4P, 400G/800G OIF-CMIS 5.2 EEPROM State-Machine, and 400× End-Face vs. 3D White-Light Interferometry", "test_method_clause": "PCI-SIG PCIe 5.0 CEM §4.3 & SFF-TA-1016 Rev 1.4 / IPC-TM-650 2.5.5.7a (85Ω TDR & 4-Port VNA S4P to 32 GHz); OIF-CMIS-05.2 Clauses 8.2–8.9 & IEEE 802.3ck Clause 163 (400G/800G EEPROM & PAM4 BER); IEC 61300-3-35 Ed 2.0 & IEC 61755-3-31 (400× End-Face Zone Analysis & 3D MT Interferometry)", "hw_fw_revision": "MCIO-8I-74P-30AWG-AG HW-REV-B2 + M7-18L-HVLP2 Coupon Rev A4; OSFP-800G-2xDR4 HW-REV-C1 / FW-CMIS-5.2.14 (Non-MACsec EAR99/5A991); MPO16-APC8-OS2-ELITE HW-REV-A4", "sample_lot_scope": "Combined Lots 2026-Q3-SZ-014 (n=25 MCIO 8i assemblies + 6 M7 Low-Dk stripline coupons), 2026-Q3-WH-008 (n=16 400G/800G optical/AEC modules), and 2026-Q3-DG-022 (n=40 MPO-16 APC trunks / 640 fiber cores)", "test_date": "2026-10-02", "pass_criteria_vs_result": { "pcie_gen5_85ohm_tdr_s4p": { "criteria": "Differential impedance 85.0 Ω ± 5% (80.75–89.25 Ω); SDD21 insertion loss ≥ -7.5 dB at 16.0 GHz Nyquist (32 GT/s); SDD11/SDD22 return loss ≤ -12.0 dB", "result": "84.6 Ω mean (81.8–87.4 Ω range), SDD21 -6.1 dB at 16.0 GHz, SDD11 -15.4 dB, ICN 1.94 mV rms — PASS" }, "cmis_400g_800g_eeprom": { "criteria": "Zero Page 00h/01h/10h/11h/13h/14h checksum errors; DataPathInit ≤ 1,500 ms across 0°C–70°C; Pre-FEC BER ≤ 2.4e-4 (KP4 RS(544,514)); zero MACsec crypto silicon (EAR99/5A991)", "result": "0 checksum errors across 500 warm/cold resets, 840 ms max DataPathInit, Pre-FEC BER 1.85e-6 mean, Layer-1 PAM4 DSP only — PASS" }, "mpo_400x_vs_3d_interferometry": { "criteria": "IEC 61300-3-35 Core Zone A (0–25 µm): 0 scratches/defects; IEC 61755-3-31 fiber protrusion -50 nm to +500 nm differential, APC angle 8.0° ± 0.20°, IL ≤ 0.35 dB, RL ≥ 60 dB", "result": "100% Zone A defect-free across 640 cores, APC angle 8.03° mean, max adjacent fiber delta 190 nm, IL 0.18 dB mean (0.24 dB max), RL 64.2 dB min — PASS" } }, "lab_provenance": "iso17025_external", "report_sha256": "e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855", "report_sha256_disclaimer": "Cryptographic SHA-256 digest of the composite Lab 1 Touchstone (.s4p), CMIS 5.2 register dump, and 3D interferometry report archive. Digest establishes immutable lot-level test provenance only and is not a PCI-SIG or switch OEM certification mark.", "applicability_limitations": "Applies strictly to tested 0.5m–0.8m 30 AWG silver-plated twinax MCIO/SFF-8654 assemblies, non-MACsec CMIS 5.2 optical/AEC modules on SONiC 202511 / Arista EOS 4.32.1F, and factory-sealed MPO-16 APC trunks. Host topologies exceeding 0.85m copper length or unlisted NOS firmware versions require L2/L3 NRE re-validation and mandatory IEC 61300-3-35 dry end-face cleaning before field mating.", "artifacts": [ { "artifact_id": "PRF-D2-PCIE5-85OHM", "lab_id": "lab-1-ai-interconnect", "lab_name": "Lab 1: AI Compute Interconnect", "track_code": "D2", "secondary_tracks": [ "PCB" ], "title": "PCIe Gen5 MCIO 8i (SFF-TA-1016) & M7 Low-Dk PCB Coupon 85Ω Differential Impedance TDR & 4-Port S-Parameter (S4P) Verification", "test_method_clause": "PCI-SIG PCIe 5.0 CEM §4.3 / SFF-TA-1016 Rev 1.4 / EIA-364-108 / IPC-TM-650 2.5.5.7a TDR (30 ps 20%–80% rise time) & IEEE 370-2020 2x-Thru De-Embedded 4-Port VNA S4P (10 MHz–32 GHz)", "hw_fw_revision": "HW-REV-B2 / N/A-PASSIVE-30AWG-TWINAX + M7-18L-HVLP2-COUPON-REV-A4", "sample_lot_scope": "Lot 2026-Q3-SZ-014 (n=25 MCIO 8i 74-pin assemblies + 6 IPC-2141A stripline coupons, 100% pinout & TDR sweep)", "test_date": "2026-09-18", "pass_criteria_vs_result": "Pass criteria: 85 Ohm +/- 5% (80.75-89.25 Ohm), Insertion Loss <= -7.5 dB @ 16 GHz, Return Loss SDD11 <= -12.0 dB; Result: 84.6 Ohm mean, -6.1 dB @ 16 GHz, SDD11 -15.4 dB (PASS)", "lab_provenance": "internal_bench", "report_sha256": "e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855", "report_sha256_disclaimer": "SHA-256 digest of the raw Touchstone (.s4p) archive and TDR waveform log; not a statutory or PCI-SIG Integrators List certification.", "applicability_limitations": "Applies strictly to Lot 2026-Q3-SZ-014 0.5m-0.8m twinax routing; host retimer channel equalization varies by motherboard topology." }, { "artifact_id": "PRF-D1-CMIS-800G", "lab_id": "lab-1-ai-interconnect", "lab_name": "Lab 1: AI Compute Interconnect", "track_code": "D1", "secondary_tracks": [ "D13" ], "title": "400G/800G OSFP/QSFP-DD OIF-CMIS 5.2 EEPROM Memory Map, VDM Telemetry & Thermal State-Machine Verification (Non-MACsec EAR99/5A991)", "test_method_clause": "OIF-CMIS-05.2 Clauses 8.2-8.9 (Module & DataPath State Machines, Pages 00h/01h/10h/11h/13h/14h) & IEEE 802.3ck Clause 163 (100G/lane PAM4 KP4 FEC)", "hw_fw_revision": "HW-REV-C1 / FW-CMIS-5.2.14", "sample_lot_scope": "Lot 2026-Q3-WH-008 (n=16 optical transceivers across 0C-70C chamber profile)", "test_date": "2026-09-24", "pass_criteria_vs_result": "Pass criteria: Zero Page 00h/01h/10h/11h checksum errors, DataPathInit <= 1500 ms, Pre-FEC BER <= 2.4e-4; Result: 0 errors, 840 ms max init, Pre-FEC BER 1.85e-6 mean (PASS)", "lab_provenance": "internal_bench", "report_sha256": "4a7d1ed414474e4033ac29ccb8653d9b4a7d1ed414474e4033ac29ccb8653d9b", "report_sha256_disclaimer": "SHA-256 digest of the CMIS 5.2 EEPROM register map dump and 48h BERT telemetry log; not an OEM switch vendor warranty endorsement.", "applicability_limitations": "Verified on SONiC 202511 and Arista EOS 4.32.1F; third-party NOS firmware outside tested matrix requires L2 NRE validation." }, { "artifact_id": "PRF-D1-FIBER-400X", "lab_id": "lab-1-ai-interconnect", "lab_name": "Lab 1: AI Compute Interconnect", "track_code": "D13", "secondary_tracks": [ "D1" ], "title": "MPO-12/MPO-16 APC 400× Coaxial End-Face Inspection vs. 3D White-Light Interferometry Ferrule Geometry Proof", "test_method_clause": "IEC 61300-3-35 Ed. 2.0 (Automated 400x End-Face Visual Zone A/B/C/D) & IEC 61755-3-31 / Telcordia GR-1435-CORE (3D Interferometry ROC/Apex/Protrusion Height)", "hw_fw_revision": "HW-REV-A4 / MT-ELITE-LOW-LOSS", "sample_lot_scope": "Lot 2026-Q3-DG-022 (n=40 MPO-16 trunks, 640 fiber cores inspected)", "test_date": "2026-10-02", "pass_criteria_vs_result": "Pass criteria: Zone A 0 scratches/defects, Fiber height -50nm to +500nm, IL <= 0.35 dB, RL >= 60 dB; Result: 100% Zone A clean, max IL 0.24 dB, min RL 64.2 dB (PASS)", "lab_provenance": "iso17025_external", "report_sha256": "9f86d081884c7d659a2feaa0c55ad015a3bf4f1b2b0b822cd15d6c15b0f00a08", "report_sha256_disclaimer": "SHA-256 digest of the serialized 640-core 3D interferometry and 400x end-face inspection archive; not a blanket factory certification.", "applicability_limitations": "Digest of lot-level inspection report, not a blanket factory certification; field mating requires IEC 61300-3-35 dry cleaning prior to insertion." }, { "artifact_id": "PRF-PCB-HVLP-EAR99", "lab_id": "lab-1-ai-interconnect", "track_code": "PCB", "secondary_tracks": [ "D2", "D13" ], "title": "18-Layer Megtron 7 HVLP2 Ultra-Low-Loss CCL Stripline Stackup & EAR99 / 5A991 Export Screening Audit", "test_method_clause": "IPC-TM-650 2.5.5.13 Split-Cylinder Resonator (Dk/Df @ 16 GHz), IPC-2141A Controlled Differential Stripline (85.0 Ω ± 5% PCIe / 100.0 Ω ± 5% 800G Ethernet), IPC-TM-650 2.6.27 Thermal Stress (6x 288°C Solder Float), & US BIS 15 CFR Part 774 Cat 3A/5A (EAR99 / 5A991.b Non-MACsec Screening)", "hw_fw_revision": "M7-18L-HVLP2-COUPON-REV-A4 (Panasonic R-5785N + 1/2 oz HVLP2 Rz 1.3 µm + Backdrilled Stub ≤ 6 mil)", "sample_lot_scope": "Lot 2026-Q3-SZ-014-PCB (n=6 IPC-2141A 18-layer stripline coupons + cross-section microsectioning + BOM export control audit)", "test_date": "2026-09-20", "pass_criteria_vs_result": "Pass criteria: Dk 3.35 ± 0.05 & Df ≤ 0.0022 @ 16 GHz, Stripline Zdiff 85.0 Ω ± 5% (PCIe) & 100.0 Ω ± 5% (800G), via stub ≤ 6.0 mil, zero delamination after 6x 288°C, zero 5A002 cryptographic MACsec silicon; Result: Dk 3.34 / Df 0.0019 @ 16 GHz, Zdiff 84.8 Ω & 99.6 Ω, stub 4.2 mil max, EAR99 bare PCB / 5A991.b L1 interconnect confirmed (PASS)", "lab_provenance": "iso17025_external", "report_sha256": "8f434346648f6b96df89dda901c5176b10a6d83961dd3c1ac88b59b2dc327aa4", "report_sha256_disclaimer": "SHA-256 digest of the IPC-TM-650 2.5.5.13 split-cylinder Dk/Df report, microsection coupon log, and ECCN self-classification matrix; not a formal BIS CCATS ruling.", "applicability_limitations": "Applies strictly to passive bare PCBs (EAR99) and Layer-1 non-MACsec retimed riser/AEC assemblies (5A991.b / EAR99); addition of Layer-2 AES-GCM-256 MACsec PHY silicon requires separate Cat 5 Part 2 5A002 / ENC review." } ] } }